1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuits, and more particularly, to a semiconductor chip capable of implementing wire bonding over active circuits (also referred to as “BOAC”) and including capacitors situated beneath a bonding pad structure.
2. Description of the Prior Art
Accompanying progress of semiconductor technology, critical dimensions of integrated circuits are continually shrunk. Therefore, bonding pads which spread around on a chip are obstacles for reducing the chip size. A person skilled in the art understands that active circuits in general are not permitted to be disposed underneath a bonding pad since chip manufacturers and designers agree on the need to avoid damaging integrated circuits disposed underneath a bonding pad with mechanical stress during bonding. Furthermore, the requirements for functional chips and system on a chip (SOC) have increased recently, so how to appropriately disperse mechanical stress acting on a chip during bonding and how to effectively utilize space underneath a bonding pad for implementing wire bonding over active circuits or specific circuits and shrinking a chip size are important for chip manufacturers and designers. For this reason, implementing wire bonding over active circuits is a trend for chip design and manufacturing.
Please refer to FIG. 1. FIG. 1 is a top view of a BOAC integrated circuit structure according to the prior art. A semiconductor chip 10 includes a core area 12 in its central region. A plurality of active devices (not shown) are formed beneath the core area 12. The semiconductor chip 10 further includes a plurality of bonding pads 14 arranged therein. For preventing mechanical stresses from damaging circuits and devices (not shown) beneath the bonding pad 14 during bonding, a portion of specific devices such as a capacitor 16 are disposed between the bonding pad 14 and the core area 12. For solving the disadvantage of the space underneath the bonding pad 14 being unable to be utilized effectively, U.S. Pat. No. 6,476,459 assigned to Korea Samsung Electronics Ltd. discloses an integrated circuit structure including capacitors formed underneath bonding pads. The capacitor structure includes two different potential conductors stacked on different levels and a dielectric located between the two conductors for forming a capacitor for improving the space utilizing underneath bonding pads.
However, U.S. Pat. No. 6,476,459 has disadvantages of the supporting structure being weaker and the manufacturing process being too complex. Therefore, how to utilize same plane conductors to form capacitors and reinforce the supporting structure during bonding is the key point of the present invention.